1. Field of the Invention
The present invention relates to a method for defining lines in an integrated circuit level. More specifically, the present invention relates to a line decomposition method, compatible with any method for defining high-density lines used in integrated circuits. The present invention also relates to an integrated circuit comprising an interconnection level obtained by the disclosed manufacturing method.
2. Discussion of Prior Art
Many methods for defining lines in integrated circuit levels are known. Such methods may for example be used to define locations of etched area in which a conductive material is deposited to form tracks, for example, conductive interconnection tracks of an integrated circuit. They may also be used for the definition of any element formed in an integrated circuit and having a significant density, for example, transistor gates.
Generally, such methods comprise forming, at the surface of the area to be etched, an etch mask also called hard mask. A hard mask may for example be obtained by performing steps of photolithography of a resin deposited at the surface of a hard mask layer and then etching portions of the hard mask through the resin mask.
Once the hard mask has been formed, locations of conductive tracks and vias of an interconnection level may be etched, for example, by a damascene process, to then carry out a single step of deposition of a conductive material and form tracks and vias of a same level.
To obtain lines having a greater density, at the surface of a circuit, the density of the openings in the hard mask must be increased. However, current photolithography and hard mask etching techniques do not enable to form etched regions of an etch mask very close to one another. Indeed, openings defined in resin masks defined by photolithography, and thus in hard masks, cannot have dimensions smaller than a threshold defined by the methods for manufacturing these masks.
To solve this problem, it has been provided to form etched lines through a hard mask defined in several steps, for example, by carrying out two steps of etching through two resin masks defined by two separate photolithography steps: a first resin mask has openings corresponding to parallel lines of even rank, a second resin mask has openings corresponding to parallel lines of odd rank.
A disadvantage of the hard mask definition method implementing two steps of etching through two resin masks defined by two photolithography steps is that the resin masks must be perfectly aligned to obtain conformal line etchings. Indeed, a poor alignment between resin masks implies variable distances between lines, which may cause electric problems in the integrated circuit interconnection levels (in the case of lines filled with a conductive material). In practice, such an alignment is very difficult to obtain with a sufficient accuracy for the densest lines.
Other techniques for forming lines etched through an etch mask defined in two steps (known under acronym DPT, for Dual Patterning Technique) have been provided. One of these techniques is known as the SIT, for Sidewall Image Transfer.
FIGS. 1A to 6A, respectively 1B to 6B, illustrate in cross-section views, respectively in top views, steps of a method for defining lines etched through an etch mask defined in two steps, of SIT type.
At the step illustrated in FIGS. 1A and 1B, it is started from a device comprising a support 10 at the surface of which a layer 12 in which lines are desired to be defined is provided. On layer 12 is formed a sacrificial layer 14, having, provided at its surface, resin pads 16 previously etched by photolithography so that they correspond to a first set of lines which are desired to be defined in layer 12.
At the step illustrated in FIGS. 2A and 2B, sacrificial layer 14 is etched through resin pads 16, which forms pads 18 at the surface of layer 12. Resin 16 is then removed.
At the step illustrated in FIGS. 3A and 3B, a layer 20 of a material selectively etchable over layer 12 and over portions 18 is conformally formed over the entire device.
At the step illustrated in FIGS. 4A and 4B, conformal layer 20 has been anisotropically etched so that it only leaves portions forming spacers 22 along portions 18. Exposed portions 18 are then removed.
An etch mask defining a first set of openings 24 at the location of portions 18 and a second set of openings 26 at the level of portions where layer 20 has been removed from the surface of layer 12 to be etched is then obtained at the surface of layer 12 to be etched.
At the step illustrated in FIGS. 5A and 5B, and etch (transfer) step has been carried out. This step comprises etching layer 12 through the etch mask defined by portions 22. Layer 12 is etched at the level of openings 24 and 26.
To properly define the ends of the lines, the etching of layer 12 is performed through a mask 28 (see FIG. 4B) having its contour corresponding to the ends of the lines which are desired to be defined. The stopping of the line etching may also be obtained by other techniques.
At the step illustrated in FIGS. 6A and 6B, trenches 32 have been filled with a conductive material 34 to form conductive tracks. In FIGS. 6A and 6B, tracks 34 formed in front of openings 24 and tracks 34 formed in front of openings 26 have been shown with hatchings. Indeed, it is generally considered that lines 32 obtained at the level of openings 24 and 26 (formed at two different steps of the method for defining the hard etch mask) are not associated with a same step of definition of the hard mask, and thus, by extension, that there are “two” steps of line definition (although the final transfer is performed at the same time for all lines). It is also currently spoken of different colors for tracks 34 associated with openings 24 and tracks 34 associated with openings 26.
In the following description, this color terminology will be used to designate, with a first color, all the lines or tracks defined in front of openings 24 and, with a second color, all the lines or tracks defined in front of openings 26.
This color terminology similarly applies to any etch mask definition method of DPT (Dual Patterning Technique) type, or to methods implementing two steps of resin mask definition by photolithography to form the hard etch mask. Thus, lines of a first color, respectively of a second color, are lines corresponding to openings formed in the etch/transfer mask in a first step, respectively in a second step, of definition of the etch/transfer mask.
Thus, when a line pattern is defined, it is necessary to perform a step of “coloring” of the different lines or line portions to assign them a color and ensure their practical forming.
FIG. 7 illustrates a disadvantage of a dual DPT-type etching method or of a double photolithography method, for example, of the method described in relation with FIGS. 1A to 6A and 1B to 6B, in the case of specific lines.
In FIG. 7, an assembly of conductive tracks of two colors (two types of hatchings) is shown at the surface of a support 40. The tracks of a first color correspond to a first etch mask definition step and the tracks of a second color correspond to a second etch mask definition step.
The use of DPT-type methods, or of methods of etch mask definition by double photolithography, implies that lines of different colors are alternately formed at the surface of support 40 (lines C1 for the first color, C2 for the second color).
In the example of FIG. 7, tracks 42-1 (on a line C1) and 42-2 (on a line C2) extend at the surface of structure 40 along one line only (one-dimensional structure, 1D). Other tracks 44-1, 44-2, are formed of two portions located in different lines, but of same rank (C1 or C2), connected by perpendicular connection tracks (two-dimensional structure, 2D). In this case, the connection track is formed during the same step as that defining the parallel line portions to be connected.
A coloring issue 48 arises when a line portion 46-1 located on a line of even rank C1 is desired to be connected to a line portion 46-2 located on a line of odd rank C2 (specific 2D structure).
To overcome this problem, a manual adjustment of the line pattern may be provided, to locally modify the line positioning in problem areas. However, a manual adjustment cannot be envisaged at the scale of a complex finite electronic circuit.
Another solution would be to forbid 2D structures which raise issues, that is, which have their two parallel portions separated by an even number of lines. This solution however implies using other means to connect these two lines, for example, in the case of a stack of integrated circuit interconnection levels, by running through an adjacent interconnection level and by forming conductive vias. This may however complicate the system manufacturing, or further decrease the track density.
There is a need for a line definition method overcoming the above-mentioned problems of connection between lines of an assembly of parallel lines defined in an integrated circuit. There thus is a need for a method for defining lines capable of being colored.